The present invention relates to very large scale integrated circuits, and to methods for fabrication thereof.
Interconnect technology is increasingly a major limitation in the fabrication of very large scale integrated circuits. In particular, the use of multiple patterned polysilicon or metal layers for interconnects places great pressure on the processing technology related to etching of contact holes and planarization of interlevel dielectrics. However, the additional routing capability which is provided by any additional level of interconnect will often give circuit designers options which translate into more compact layouts, better circuit performance, and/or greater ease of circuit design.
For these reasons much effort has been dedicated to modifying processes to include a buried contact. A buried contact process is a process which uses a single layer to form not only MOS gates, but also, using other patterned portions of the same layer, contact to the source/drain regions of MOS transistors. That is, the same thin film polysilicon or polycide layer must in some locations be separated from the moat by a very thin high-integrity gate oxide, and in other locations must form an ohmic contact to highly doped moat regions. This leads to three main classes of processing problems: first, gate oxide integrity becomes more difficult to preserve. Second, scalability is limited by interdiffusion between the polysilicon material and the bulk silicon. That is, the phosphorus doping used to make the polysilicon conductive will normally outdiffuse into the silicon substrate at the contact location. However, as devices are scaled to small geometries, this phosphorus diffusion can counterdope a major fraction of the channel stop doping, leading to leakage between active areas. Third, first contacts are highly desirable in CMOS processing, but present technology does not provide any manufacturable process to make contact to P+ moat regions. Not only is there the problem of how to avoid a diode between N+ poly and P+ substrate, but similar problems of dopant outdiffusion may lead to shorting from the poly to the PMOS substrate at first contacts to P+.
There have been published suggestions of ways to provide a local interconnect level in the context of a self-aligned titanium silicide process for source/drain silicidation. The self-aligned titanium silicide source/drain silicidation process is disclosed in U.S. patent application Ser. No. 492,069, filed May 6, 1983, (TI-9596), which is hereby incorporated by reference. In this process, metallic titanium is deposited overall, and is then heated in a nitrogen atmosphere so that the titanium reacts with exposed silicon surfaces (such as source/drain regions, or exposed upper surfaces of polysilicon lines) to form titanium silicide. The portions of titanium which did not react to form silicides are then stripped (using, for example, a wet etch). This process provides a self-aligned silicidation process without any patterning steps. This self-aligned silicidation process has come into wide use in integrated circuit fabrication.
In a 1985 IEDM paper, researchers from Hewlett-Packard proposed applying a sputtered silicon layer over the deposited titanium metal, in a direct-react titanium silicidation process, before the reaction step, to provide patterned local interconnects of titanium silicide. These local interconnects were apparently thought at the time to provide advantages comparable to that of the titanium nitride interconnect of the present invention. However, not only does this approach require greater processing complexity, but it also fails to provide a crucial advantages of the present invention: the titanium silicide provides an efficient diffusion path for boron and phosphorous, and therefore problems of interdiffusion and counterdoping remain acute. By contrast, in the present invention the titanium nitride is a very good diffusion barrier, and these problems do not arise. The phosphorus counterdoping problems of the process shown in the HP 1985 paper may be confirmed by a more recent HP paper which describes a 16K static random access memory implemented with their TiSi.sub.2 strap process, but that only uses it to connect P-type and N-type junctions together. That is, the HP researchers did not use local interconnect to connect gates to junctions. In a design experiment to test the advantages of the present invention, researchers at Texas Instruments laid out a static random access memory cell according to the exact HP layout, i.e. where local interconnect is used to interconnect junctions, and where metal straps plus 2nd contacts are used to cross-couple the gates. In this HP process, the inability to interconnect both the gates and junctions with local interconnect results in a cell size, using 1 micron design rules, that is 75% larger than a cell with the same design rule geometries using TiN for local interconnect. This illustrates the advantage that TiN has over TiSi.sub.2 for performing the local interconnect function.
The previously proposed local interconnect schemes based on this process use additional patterned silicon to provide conductive silicide regions extending out over the field oxide as desired. That is, in the process developed by Hewlett Packard and published at Page 118 of the 1984 IEDM Proceedings, (which publication is hereby incorporated by reference), after the titanium metal is deposited overall, and before heat is applied to effect silicide reaction, a thin layer of silicon (either polycrystalline or amorphous) is patterned on top of the titanium metal. Where this silicon layer has been applied, a silicide will form during the reaction process, so that silicides can be formed extending over the gate sidewall oxide or over the field oxide. A similar approach previously developed at Texas Instruments used patterned silicon straps which were applied before the titanium metal was applied.
However, both of these approaches have the limitation that deposition of an additional layer is required. Thus, both of these approaches contain excess processing complexities.
Other publications relevant to examination of the present application may be found in the paper by C. Y. Ting at page 110 of the 1984 IEDM proceedings (and see especially page 113) and in the paper by M. Alperin et al., Development of the Self-aligned TiSi.sub.2 Process for VLSI applications, at page 141 of the February 1985 issue of the IEEE transactions on Electron Devices.
The present invention provides a simpler method of forming local interconnects in the context of a self-aligned direct-react titanium silicide process for source/drain (and preferably gate) silicidation.
It has been discovered that when the direct-react titanium silicide silicidation process is performed in a nitrogen atmosphere, a layer of titanium nitride (TiN) is formed in the titanium metal layer over field oxide. Thus, after the silicide reaction occurs, the portions of the deposited titanium metal layer which have not been in contact with a source of silicon (and therefore have not formed silicide) are not merely unreacted titanium metal, as was previously thought, but include a large fraction of titanium nitride. The present invention makes use of this newly discovered titanium nitride layer to provide a new and advantageous local interconnect method and structure.
After the silicidation step, the titanium nitride layer can be patterned and selectively removed from titanium silicide and silicon oxide regions where it is not desired. (Preferably the thickness of the TiN layer will be increased before the patterning step, as described below.) After this, a final anneal is performed at higher temperature (e.g. 800 C.) to reduce the final sheet resistance of the titanium silicide layers to below one ohm per square.
It is well-known in the integrated circuit art that titanium nitride is conductive, and the use of titanium nitride as a conductive diffusion barrier in contacts has been previously published; but no work published prior to the filing date of the parent application is known to discuss the use of titanium nitride to provide local interconnects, as in the present invention.
As discussed above, TiN is tremendously useful, as a moat cladding to decrease the series resistance of MOS devices, as a polysilicon cladding to decrease the resistance of polysilicon lines, as a local interconnect material, and as a good diffusion barrier for various dopants. However, these multiple uses place some conflicting demands on the processing conditions: Because TiN (in the whole class of presently preferred embodiments) is a by-product of the direct react TiSi.sub.2 process, its thickness is determined by the thickness of the deposited Ti; but this thickness is controlled by the device requirements for silicide thickness, which result from factors such as junction depth, stress of the TiSi.sub.2 film, current profiles, and electric field profiles. As CMOS devices continue to scale down and shallow source/drain junctions are used, thinner TiSi.sub.2 thickness must be used, and therefore thinner Ti deposition is required. This means that thinner TiN will be produced. This thinner TiN layer has higher sheet resistance, which makes the TiN less desirable as an interconnect material. Moreover, a thinner TiN layer will be less effective as an etch stop at the bottom of contact holes. Moreover, a thinner TiN layer (if sufficiently thin) will also be less effective as a diffusion barrier at the bottom of contact holes (to prevent diffusion of silicon, metal, or dopants between the contact metal and silicon).
The present inventive embodiment solves these constraints by providing a process where the TiN thickness is increased to any desired value without affecting the thickness of TiSi.sub.2. The additional process steps used to fabricate the thicker TiN layer are simple and compatible with present CMOS technology.
By depositing a second layer of titanium (or other suitable metal) after the first layer has been heated in a nitrogen atmosphere, the TiN at the surface of the composition formed by the first reaction will form a diffusion barrier which assures that the products of the second reaction are nearly all TiN.
The inventive process for increasing TiN thickness has at least the following advantages:
1. This process is fully compatible with present existing CMOS technology, and therefore requires no new fabrication techniques.
2. The thicknesses of TiSi.sub.2 and TiN are independently controlled by the successive depositions of Ti and thermal reactions, providing greater freedom in optimizing a process. This is important when shallow source/drain junctions are used and the requirement on TiN sheet resistance be fulfilled.
3. In a process which obtains all the advantages of a TiN local interconnect, the TiSi.sub.2 layer on the surfaces of the source/drains can be selected to be as small as desired, without sacrificing the sheet resistance of the TiN local interconnect lines.
4. In a process which obtains all the advantages of a TiN local interconnect, including use of the TiN layer at the bottoms of contact holes, the TiSi.sub.2 layer on the surfaces of the source/drains can be selected to be as small as desired, without sacrificing the etch stop characteristics of the TiN at the bottom of contact holes.
5. In a process which obtains all the advantanges of a TiN local interconnect, including use of the TiN layer at the bottoms of contact holes, the TiSi.sub.2 layer on the surfaces of the source/drains can be selected to be as small as desired, without sacrificing the diffusion barrier characteristics of the TiN at the bottom of contact holes.
This provides a structure wherein moat-to-moat interconnections have been formed using a very thin (e.g. 1000 Angstroms) layer of titanium nitride. This invention provides at least the following advantages:
1. Processing is simpler than in the methods for forming titanium silicide local interconnects discussed above.
2. Since titanium nitride is a very good diffusion barrier, problems of interdiffusion through the silicide are avoided. This is particularly advantageous where the local interconnect layer is used to connect a p+ moat region to an n+ polysilicon gate or to an n+ moat region in CMOS processing.
3. Titanium nitride local interconnects according to the present invention are most especially advantageous in providing local interconnect between an n+ polysilicon gate and a p-type moat region. Since the distances from gate to moat are typically much shorter than the n+ to p+ spacings, interdiffusion is a particularly acute problem here.
4. Since the titanium nitride local interconnect layer can be made extremely thin, the amount of additional vertical topography induced in subsequent unplanarized layers is minimal.
5. Since the titanium nitride layer is so thin, the etch used to remove it need not be anisotropic, which again simplifies processing.
6. Even a very thin titanium nitride layer can provide very low sheet resistances, of the order of five to ten ohms per square.
7. The titanium nitride local interconnect layer can also be utilized to provide a diffusion barrier in place for contacts. That is, contacts to moat can deposit metal on top of the titanium nitride layer rather than directly on silicon, so that interdiffusion between metal and silicon is effectively prevented. This simplifies the selection of interconnect metallization. In particular, use of non-aluminum metallization now becomes much more practical.
8. The overlap of the titanium nitride onto the field oxide means that the contact holes need not be perfectly aligned to the edge of the moat, but the contact hole can overlap onto the titanium nitride over the upper surface of the edge of the field oxide.
9. The present invention provides a local interconnect layer of such good conductivity that strapping can be avoided in some applications, and thus the present invention will permit the elimination of double-level metal (DLM) process steps in some processes, without any sacrifice of speed or area.
10. The number of second contacts in a layout can be reduced, since independent interconnection through the TiN layer can substitute for some metal interconnects.
11. The present process is inherently amenable to shared contacts, i.e. to contacts where contact is made between two interconnect layers and substrate at the same location. This permits designers additional flexibility.
12. The methods using silicon straps for local interconnect are inherently susceptible to open circuit defects where the silicon strap crosses the angle at the foot of the gate, and, to avoid this, the silicon straps need to be made relatively thick (as much as 2500 A thick in some processes), which degrades topography and throughput. By contrast, the TiN straps of the present invention do not have this problem, and therefore do not need to be made so thick.
13. Titanium nitride is more resistant to oxide etches than titanium silicide is, so that damage caused by overetching the multilevel oxide at the contact etch step in a process using a planarized multilevel oxide are reduced.
14. The capablility of overlapping moat contacts up onto the field oxide means that minimum geometry can be used for the source/drain regions in the moat.
15. The present invention permits connection between stages of CMOS logic to be accomplished without any contact holes, which provides advantages in area, speed, and yield.
16. The present invention performs all the functions of a full buried contact capability, without the degradation in gate oxide integrity which commonly results from buried contact processes.
17. The present invention performs all the functions of a full buried contact capability, without the degraded reproducibility of series resistance for ohmic contacts to p+ which commonly results from buried contact processes.
18. The present invention performs all the circuit functions of a full buried contact capability, without the problem of shorting to an underlying n+ region where a local connection from polysilicon to a p+ source/drain region.
According to the present invention there is also provided: A process for forming conductive layers on the surface of an integrated circuit device, comprising the steps of:
1. providing a partially fabricated integrated circuit structure;
2. depositing a first metal layer overall, said first metal layer predominantly comprising titanium;
3. heating said partially fabricated integrated circuit structure in a nitrogen-bearing ambient, whereby at least surface portions of said metal everywhere react to form a composition including (at least at the surface thereof) a substantial fraction of nitrides;
4. depositing a second metal layer overall, said second metal layer also predominantly comprising titanium;
5. heating said partially fabricated integrated circuit structure in a nitrogen-bearing ambient, whereby said second metal layer everywhere reacts to form a composition consisting essentially (at least at the surface thereof) of nitrides;
6. patterning and etching the conductive layer formed by said steps of reacting said first and second metal layers to form conductive lines in a predetermined pattern.